Energy Recovery and Logical Reversibility in Adiabatic CMOS Multiplier
نویسندگان
چکیده
Overcoming the IC power challenge requires signal energy recovery, which can be achieved utilizing adiabatic charging principles and logically reversible computing in the circuit design. This paper demonstrates the energyefficiency of a Bennett-clocked adiabatic CMOS multiplier via a simulation model. The design is analyzed on the logic gate level to determine an estimate for the number of irreversible bit erasures occurring in a combinatorial implementation, showing considerable potential for minimizing the logical information loss.
منابع مشابه
QSERL: Quasi-Static Energy Recovery Logic
A new Quasi-Static Energy Recovery Logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic are dynamic and require complex clocking schemes. The proposed Quasi-Static energy recovery logic uses two complementary sinusoidal supply clocks and resembles behaviors of static CMOS. Thus, switching activity is signiican...
متن کاملAn 8 x 8-b nRERL Serial Multiplier for ultra-low-power applications
| An 8 x 8-b nRERL serial multiplier is implemented in a 0.6m n-well 3-metal CMOS process. nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit, which can be operated at the leakage-current level for ultralow-energy applications. Measurement results showed that the nRERL serial multiplier consumed only 0.9 % of the energy dissipation of the static CMOS one a...
متن کاملDesign and Analysis of Asynchronous 16*16 Adiabatic Vedic Multiplier Using ECRL and EEAL Logic
In this paper, we describe adiabatic Vedic multiplier using efficient charge recovery logic (ECRL) and energy efficient adiabatic logic (EEAL). In today’s world low power hindrance have become a major important factor in modern VLSI design. Because of the increasingly draconian demands for battery space and weight in portable multimedia devices, energy productive and high yielding circuits are ...
متن کاملDesign and Implementation of Multiplier Using CMOS Adiabatic Logic
The paper presents a Power consumption plays an important role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopting different design styles. Multipliers play a major role in high performance systems. This project focuses on a novel energy efficient technique called adiabatic logic which is based on energy recovery principle and power is compar...
متن کاملLSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier
Keywords: Low-power Adiabatic logic Energy recovery Multiplier a b s t r a c t As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity ...
متن کامل